Please use this identifier to cite or link to this item: https://doi.org/10.1109/VLSIT.2007.4339719
Title: Beneath-the-channel Strain-Transfer-Structure (STS) and embedded source/drain stressors for strain and performance enhancement of nanoscale MOSFETs
Authors: Ang, K.-W.
Lin, J.
Tung, C.-H.
Balasubramanian, N.
Samudra, G. 
Yeo, Y.-C. 
Issue Date: 2007
Citation: Ang, K.-W., Lin, J., Tung, C.-H., Balasubramanian, N., Samudra, G., Yeo, Y.-C. (2007). Beneath-the-channel Strain-Transfer-Structure (STS) and embedded source/drain stressors for strain and performance enhancement of nanoscale MOSFETs. Digest of Technical Papers - Symposium on VLSI Technology : 42-43. ScholarBank@NUS Repository. https://doi.org/10.1109/VLSIT.2007.4339719
Abstract: We report the first demonstration of a novel transistor structure featuring a beneath-the-channel strain-transfer-structure (STS) and embedded source/drain (S/D) stressors for strain and performance enhancement. As compared to a transistor with standard S/D stressors, additional strain is imparted to the channel region by the STS due to coupling of its lattice interactions with the adjacent S/D stressors and the overlying channel region. Both strained n-FET with SiGe STS and silicon-carbon (SiC) S/D, and strained p-FET with SiC STS and SiGe S/D, were realized. The Ion performance of strained n- and p-FETs with STS and S/D stressors were enhanced by 42% and 60%, respectively, over unstrained control transistors for given. DIBL of 0.15 V/V.
Source Title: Digest of Technical Papers - Symposium on VLSI Technology
URI: http://scholarbank.nus.edu.sg/handle/10635/83511
ISSN: 07431562
DOI: 10.1109/VLSIT.2007.4339719
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