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Please use this identifier to cite or link to this item: https://doi.org/10.1109/ASSCC.2013.6691078
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dc.titleAn energy-autonomous piezoelectric energy harvester interface circuit with 0.3V startup voltage
dc.contributor.authorGao, Y.
dc.contributor.authorMade, D.I.
dc.contributor.authorCheng, S.-J.
dc.contributor.authorJe, M.
dc.contributor.authorHeng, C.-H.
dc.date.accessioned2014-10-07T04:41:36Z
dc.date.available2014-10-07T04:41:36Z
dc.date.issued2013
dc.identifier.citationGao, Y.,Made, D.I.,Cheng, S.-J.,Je, M.,Heng, C.-H. (2013). An energy-autonomous piezoelectric energy harvester interface circuit with 0.3V startup voltage. Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013 : 445-448. ScholarBank@NUS Repository. <a href="https://doi.org/10.1109/ASSCC.2013.6691078" target="_blank">https://doi.org/10.1109/ASSCC.2013.6691078</a>
dc.identifier.isbn9781479902781
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/83471
dc.description.abstractA high efficiency energy-autonomous interface circuit for piezoelectric energy harvester is presented in this paper. The proposed circuit includes a negative voltage converter (NVC) with dynamic body bias control, a reconfigurable switching converter working in discontinuous conduction mode (DCM) and a clock generator. The body biasing circuit provides dynamic forward body bias control to enhance NVC conversion efficiency in low input voltage range and reduce substrate leakage under high input voltage range. A reconfigurable switching converter in DCM boost/buck-boost modes provides synthesized resistive input impedance for power matching and voltage step-up. Implemented in a standard 65nm CMOS process, the proposed system has a measured cold startup voltage of 0.3V with a maximum conversion efficiency of 70%. © 2013 IEEE.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/ASSCC.2013.6691078
dc.sourceScopus
dc.subjectActive rectifier
dc.subjectEnergy harvesting
dc.subjectPiezoelectric
dc.subjectSwitching converter
dc.typeConference Paper
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.doi10.1109/ASSCC.2013.6691078
dc.description.sourcetitleProceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013
dc.description.page445-448
dc.identifier.isiutNOT_IN_WOS
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