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|Title:||Advanced channel and contact technologies for future CMOS devices||Authors:||Yeo, Y.-C.||Issue Date:||2012||Citation:||Yeo, Y.-C. (2012). Advanced channel and contact technologies for future CMOS devices. International Symposium on VLSI Technology, Systems, and Applications, Proceedings : -. ScholarBank@NUS Repository. https://doi.org/10.1109/VLSI-TSA.2012.6210144||Abstract:||Technology options for reducing channel and contact resistances in advanced transistors will be reviewed. Strain engineering techniques for enhancing electron and hole mobilities will be discussed, e.g. novel source/drain (S/D) stressors, buried stressors, novel high stress liners, etc. Also, external series resistance R ext has become a more dominant component of the total resistance between S/D in recent years. Solutions for reducing R C will be discussed. Approaches to reduce electron and hole barrier heights between the metallic contact and S/D region will be discussed. © 2012 IEEE.||Source Title:||International Symposium on VLSI Technology, Systems, and Applications, Proceedings||URI:||http://scholarbank.nus.edu.sg/handle/10635/83442||ISBN:||9781457720840||ISSN:||19308868||DOI:||10.1109/VLSI-TSA.2012.6210144|
|Appears in Collections:||Staff Publications|
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