Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/83301
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dc.title50 nm silicon-on-insulator N-MOSFET featuring multiple stressors: Silicon-carbon source/drain regions and tensile stress silicon nitride liner
dc.contributor.authorAng, K.-W.
dc.contributor.authorChui, K.-J.
dc.contributor.authorChin, H.-C.
dc.contributor.authorFoo, Y.-L.
dc.contributor.authorDu, A.
dc.contributor.authorDeng, W.
dc.contributor.authorLi, M.-F.
dc.contributor.authorSamudra, G.
dc.contributor.authorBalasubramanian, N.
dc.contributor.authorYeo, Y.-C.
dc.date.accessioned2014-10-07T04:39:43Z
dc.date.available2014-10-07T04:39:43Z
dc.date.issued2006
dc.identifier.citationAng, K.-W.,Chui, K.-J.,Chin, H.-C.,Foo, Y.-L.,Du, A.,Deng, W.,Li, M.-F.,Samudra, G.,Balasubramanian, N.,Yeo, Y.-C. (2006). 50 nm silicon-on-insulator N-MOSFET featuring multiple stressors: Silicon-carbon source/drain regions and tensile stress silicon nitride liner. Digest of Technical Papers - Symposium on VLSI Technology : 66-67. ScholarBank@NUS Repository.
dc.identifier.isbn1424400058
dc.identifier.issn07431562
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/83301
dc.description.abstractA novel n-channel strained SOI transistor featuring siliconcarbon (SiC) source/drain (S/D) regions and tensile stress silicon nitride (SiN) liner is demonstrated for the first time. Drive current IDsat enhancement contributed by the dual stressors is found to be additive and a significant increase in IDsat of 55% is observed at a gate length LG of 50 nm. In addition, we report the dependence of drive current on channel orientation, with highest IDsat observed for strained n-MOSFETs with the [010] channel direction. A study of the carrier transport characteristics indicate reduced channel backscattering and enhanced carrier injection velocity due to the strain effects. © 2006 IEEE.
dc.sourceScopus
dc.typeConference Paper
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.sourcetitleDigest of Technical Papers - Symposium on VLSI Technology
dc.description.page66-67
dc.description.codenDTPTE
dc.identifier.isiutNOT_IN_WOS
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