Please use this identifier to cite or link to this item: https://doi.org/10.1109/LED.2011.2106757
Title: Vertical Si-Nanowire n-type tunneling FETs with low subthreshold swing ≤50 mV/decade) at room temperature
Authors: Gandhi, R.
Chen, Z.
Singh, N.
Banerjee, K.
Lee, S. 
Keywords: CMOS technology
gate-all-around (GAA)
subthreshold swing (SS)
top-down
tunneling field-effect transistor (TFET)
vertical silicon nanowire (NW) (SiNW)
Issue Date: Apr-2011
Citation: Gandhi, R., Chen, Z., Singh, N., Banerjee, K., Lee, S. (2011-04). Vertical Si-Nanowire n-type tunneling FETs with low subthreshold swing ≤50 mV/decade) at room temperature. IEEE Electron Device Letters 32 (4) : 437-439. ScholarBank@NUS Repository. https://doi.org/10.1109/LED.2011.2106757
Abstract: This letter presents a Si nanowire based tunneling field-effect transistor (TFET) using a CMOS-compatible vertical gate-all-around structure. By minimizing the thermal budget with low-temperature dopant-segregated silicidation for the source-side dopant activation, excellent TFET characteristics were obtained. We have demonstrated for the first time the lowest ever reported subthreshold swing (SS) of 30 mV/decade at room temperature. In addition, we reported a very convincing SS of 50 mV/decade for close to three decades of drain current. Moreover, our TFET device exhibits excellent characteristics without ambipolar behavior and with high Ion}/Ioff ratio (\∼ 105), as well as low Drain-Induced Barrier Lowering of ∼70 mV/V. © 2011 IEEE.
Source Title: IEEE Electron Device Letters
URI: http://scholarbank.nus.edu.sg/handle/10635/83258
ISSN: 07413106
DOI: 10.1109/LED.2011.2106757
Appears in Collections:Staff Publications

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