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dc.titleVersatile pattern generation of periodic, high aspect ratio Si nanostructure arrays with sub-50-nm resolution on a wafer scale
dc.contributor.authorHo, J.-W.
dc.contributor.authorWee, Q.
dc.contributor.authorDumond, J.
dc.contributor.authorTay, A.
dc.contributor.authorChua, S.-J.
dc.identifier.citationHo, J.-W., Wee, Q., Dumond, J., Tay, A., Chua, S.-J. (2013). Versatile pattern generation of periodic, high aspect ratio Si nanostructure arrays with sub-50-nm resolution on a wafer scale. Nanoscale Research Letters 8 (1) : 1-10. ScholarBank@NUS Repository.
dc.description.abstractWe report on a method of fabricating variable patterns of periodic, high aspect ratio silicon nanostructures with sub-50-nm resolution on a wafer scale. The approach marries step-and-repeat nanoimprint lithography (NIL) and metal-catalyzed electroless etching (MCEE), enabling near perfectly ordered Si nanostructure arrays of user-defined patterns to be controllably and rapidly generated on a wafer scale. Periodic features possessing circular, hexagonal, and rectangular cross-sections with lateral dimensions down to sub-50 nm, in hexagonal or square array configurations and high array packing densities up to 5.13 × 107 structures/mm2 not achievable by conventional UV photolithography are fabricated using this top-down approach. By suitably tuning the duration of catalytic etching, variable aspect ratio Si nanostructures can be formed. As the etched Si pattern depends largely on the NIL mould which is patterned by electron beam lithography (EBL), the technique can be used to form patterns not possible with self-assembly methods, nanosphere, and interference lithography for replication on a wafer scale. Good chemical resistance of the nanoimprinted mask and adhesion to the Si substrate facilitate good pattern transfer and preserve the smooth top surface morphology of the Si nanostructures as shown in TEM. This approach is suitable for generating Si nanostructures of controlled dimensions and patterns, with high aspect ratio on a wafer level suitable for semiconductor device production. © 2013 Ho et al.
dc.subjectMetal-catalyzed electroless etching
dc.subjectSi nanostructures
dc.subjectStep-and-repeat nanoimprint lithography
dc.subjectSub-50-nm resolution
dc.subjectUser-defined patterns
dc.subjectWafer scale
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.contributor.departmentMECHANICAL ENGINEERING
dc.description.sourcetitleNanoscale Research Letters
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