Please use this identifier to cite or link to this item: https://doi.org/10.1109/TED.2009.2019388
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dc.titleUltra high-stress liner comprising diamond-like carbon for performance enhancement of p-channel multiple-gate transistors
dc.contributor.authorTan, K.-M.
dc.contributor.authorYang, M.
dc.contributor.authorLiow, T.-Y.
dc.contributor.authorLee, R.T.P.
dc.contributor.authorYeo, Y.-C.
dc.date.accessioned2014-10-07T04:38:56Z
dc.date.available2014-10-07T04:38:56Z
dc.date.issued2009
dc.identifier.citationTan, K.-M., Yang, M., Liow, T.-Y., Lee, R.T.P., Yeo, Y.-C. (2009). Ultra high-stress liner comprising diamond-like carbon for performance enhancement of p-channel multiple-gate transistors. IEEE Transactions on Electron Devices 56 (6) : 1277-1283. ScholarBank@NUS Repository. https://doi.org/10.1109/TED.2009.2019388
dc.identifier.issn00189383
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/83239
dc.description.abstractWe report the demonstration of strained p-channel multiple-gate transistors or FinFETs with a novel liner-stressor material comprising diamond-like carbon (DLC). In this work, a DLC film with very high intrinsic compressive stress up to 6 GPa was employed. For FinFET devices having a 20 nm thin DLC liner stressor, more than 30% enhancement in saturation drain current IDsat is observed over FinFETs without a DLC liner. The performance enhancement is attributed to the coupling of compressive stress from the DLC liner to the channel, leading to hole mobility improvement. Due to its extremely high intrinsic stress value, significant IDsat enhancement is observed even when the thickness of the DLC film deposited is less than 40 nm. The DLC liner stressor is a promising stressor material for performance enhancement of p-channel transistors in future technology nodes. © 2009 IEEE.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/TED.2009.2019388
dc.sourceScopus
dc.subjectContact etch stop layer (CESL)
dc.subjectDiamond-like carbon (DLC)
dc.subjectFinFET
dc.subjectMultiple-gate
dc.subjectStrain
dc.typeArticle
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.doi10.1109/TED.2009.2019388
dc.description.sourcetitleIEEE Transactions on Electron Devices
dc.description.volume56
dc.description.issue6
dc.description.page1277-1283
dc.description.codenIETDA
dc.identifier.isiut000266330200015
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