Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/83194
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dc.titleThermal stability study of Si cap/ultrathin Ge/Si and strained Si/Si 1-xGex/Si nMOSFETs with HfO2 gate dielectric
dc.contributor.authorYeo, C.C.
dc.contributor.authorCho, B.J.
dc.contributor.authorLee, M.H.
dc.contributor.authorLiu, C.W.
dc.contributor.authorChoi, K.J.
dc.contributor.authorLee, T.W.
dc.date.accessioned2014-10-07T04:38:24Z
dc.date.available2014-10-07T04:38:24Z
dc.date.issued2006-05-01
dc.identifier.citationYeo, C.C., Cho, B.J., Lee, M.H., Liu, C.W., Choi, K.J., Lee, T.W. (2006-05-01). Thermal stability study of Si cap/ultrathin Ge/Si and strained Si/Si 1-xGex/Si nMOSFETs with HfO2 gate dielectric. Semiconductor Science and Technology 21 (5) : 665-669. ScholarBank@NUS Repository.
dc.identifier.issn02681242
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/83194
dc.description.abstractThe thermal stabilities of MOSFETs with high-K gate dielectric on both Si/ultrathin Ge/Si (SGS) and strained Si on relaxed Si1- xGex (SS) substrates are studied. Though an initial drivability enhancement of 29% is shown for the SGS nMOSFET, annealing at 750 °C has resulted in drastic degradation in its drivability, lowering its Id beyond that of the Si nMOSFETs by 52%. Despite lowering in the junction leakage current, Ge diffusion to the near surface region, indicated by Vth and surface roughness change, degrades the SGS device performance significantly. For the SS nMOSFET, drivability varies with Ge content, whereby a maximum of 86% improvement over that of the Si nMOSFET is observed for 30% Ge. In contrast to the SGS nMOSFET, the SS nMOSFET is able to retain its I d improvement, even after annealing at 950 °C, as the in-plane tensile strain is preserved. Ge diffusion to the surface does not affect the device significantly, as the strained Si thickness is about 10 nm compared to a Si cap thickness of only 1.5 nm for the SGS substrate. © 2006 IOP Publishing Ltd.
dc.sourceScopus
dc.typeArticle
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.sourcetitleSemiconductor Science and Technology
dc.description.volume21
dc.description.issue5
dc.description.page665-669
dc.description.codenSSTEE
dc.identifier.isiut000237885000019
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