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|Title:||Theoretical analysis and experimental characterization of the dummy-gated VDMOSFET||Authors:||Xu, S.
|Issue Date:||Sep-2001||Citation:||Xu, S.,Ren, C.,Liang, Y.C.,Foo, P.-D.,Sin, J.K.O. (2001-09). Theoretical analysis and experimental characterization of the dummy-gated VDMOSFET. IEEE Transactions on Electron Devices 48 (9) : 2168-2176. ScholarBank@NUS Repository. https://doi.org/10.1109/16.944212||Abstract:||In this paper, a novel silicon RF vertical double-diffusion metal-oxide-semiconductor field effect transistor (VD-MOSFET) structure with a dummy-gate incorporated between the active gates is proposed. The dummy-gate functions as a field plate to minimize the drain-to-gate feedback capacitance C rss and also to raise the device breakdown voltage. Therefore, for the same blocking voltage rating, the dummy-gate structure allows the MOSFET to have a shorter channel and a larger gate to drain overlap area to minimize the on-state resistance. Hence, the transconductance gain G m can be improved, leading to a higher RF performance for the power device. Experimental results show that with the dummy-gate a 51% lower on the feedback capacitance, a 21% lower on the on-state resistance, a 100% increase in output resistance and a higher and linear transconductance are achieved. Furthermore, the safe operating area (SOA) of the device, which is limited by the turning-on of the parasitic transistor, is improved. This allows a higher power density to be handled by the proposed device.||Source Title:||IEEE Transactions on Electron Devices||URI:||http://scholarbank.nus.edu.sg/handle/10635/83181||ISSN:||00189383||DOI:||10.1109/16.944212|
|Appears in Collections:||Staff Publications|
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