Please use this identifier to cite or link to this item: https://doi.org/10.1109/TED.2013.2255057
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dc.titleSub-400 °C Si2H6 passivation, HfO2 gate dielectric, and single TaN metal gate: A common gate stack technology for In0.7Ga0.3As and Ge1-xSnx CMOS
dc.contributor.authorGong, X.
dc.contributor.authorHan, G.
dc.contributor.authorLiu, B.
dc.contributor.authorWang, L.
dc.contributor.authorWang, W.
dc.contributor.authorYang, Y.
dc.contributor.authorKong, E.Y.-J.
dc.contributor.authorSu, S.
dc.contributor.authorXue, C.
dc.contributor.authorCheng, B.
dc.contributor.authorYeo, Y.-C.
dc.date.accessioned2014-10-07T04:37:23Z
dc.date.available2014-10-07T04:37:23Z
dc.date.issued2013
dc.identifier.citationGong, X., Han, G., Liu, B., Wang, L., Wang, W., Yang, Y., Kong, E.Y.-J., Su, S., Xue, C., Cheng, B., Yeo, Y.-C. (2013). Sub-400 °C Si2H6 passivation, HfO2 gate dielectric, and single TaN metal gate: A common gate stack technology for In0.7Ga0.3As and Ge1-xSnx CMOS. IEEE Transactions on Electron Devices 60 (5) : 1640-1648. ScholarBank@NUS Repository. https://doi.org/10.1109/TED.2013.2255057
dc.identifier.issn00189383
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/83109
dc.description.abstractWe report a novel common gate-stack solution for In0.7Ga 0.3As n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs) and Ge0.97Sn0.03 p-channel metaloxide- semiconductor field-effect transistors (pMOSFETs), featuring sub-400 °C Si2H6 passivation, sub-1.75-nm capacitance equivalent thickness (CET), and single TaN metal gate. By incorporating Si 2H6 passivation, an ultrathin SiO2/Si interfacial layer is formed between the high-k gate dielectric and the high mobility InGaAs and GeSn channels. The In0.7Ga0.3As nMOSFET and Ge0.97Sn0.03 pMOSFET show drive currents of ∼143 and ∼69μA/μm, respectively, at |VDS| and |V GS - VTH| of 1V for a gate length LG of 4μm. At an inversion carrier density Ninv of 1013 cm -2, In0.7Ga0.3As nMOSFETs and Ge 0.97Sn0.03 pMOSFETs show electron and hole mobilities of ∼495 and ∼230cm2/V·s, respectively. At Ninv of 4 × 1012 cm-2, electron and hole mobility values of ∼705 and ∼ 346cm2/V·s are achieved. Symmetric VTH is realized by choosing a metal gate with midgap work function, and CET of less than 1.75nm is demonstrated with a gate-leakage current density (JG) of less than 10-4A/cm2 at a gate bias of VTH ±1V. Using this gate-stack, a Ge0.95Sn 0.05 pMOSFET with the shortest LG of 200nm is also realized. Drive current of ∼680μA/μm is achieved at VDS of -1.5V and VGS - VTH of -2V, with peak intrinsic transconductance Gm,int of ∼492μS/μm at VDS of -1.1V. © 2013 IEEE.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/TED.2013.2255057
dc.sourceScopus
dc.subjectGeSn pMOSFET
dc.subjectInGaAs nMOSFET
dc.subjectSi2H6 passivation
dc.typeArticle
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.doi10.1109/TED.2013.2255057
dc.description.sourcetitleIEEE Transactions on Electron Devices
dc.description.volume60
dc.description.issue5
dc.description.page1640-1648
dc.description.codenIETDA
dc.identifier.isiut000319352900021
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