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Title: SDODEL MOSFET for performance enhancement
Authors: Chui, K.J.
Samudra, G.S. 
Yeo, Y.-C. 
Tee, K.-C.
Leong, K.-W.
Tee, K.M.
Benistant, F.
Chan, L.
Keywords: Junction capacitance
Issue Date: Mar-2005
Citation: Chui, K.J., Samudra, G.S., Yeo, Y.-C., Tee, K.-C., Leong, K.-W., Tee, K.M., Benistant, F., Chan, L. (2005-03). SDODEL MOSFET for performance enhancement. IEEE Electron Device Letters 26 (3) : 205-207. ScholarBank@NUS Repository.
Abstract: A high-energy, low-dose implant of the source/drain (S/D) doping type is introduced after the gate definition step to form doped regions beneath and separated from the source and drain regions to fabricate source/ drain on depletion layer (SDODEL) transistors. Under zero bias, these doped regions are fully depleted and the resulting transistor structure is termed an SDODEL MOSFET. The fully depleted regions act electrically like insulators, as in the case of silicon-on-insulator (SOI), to reduce junction capacitance. SDODEL MOSFETs with 0.16-μm gate length are fabricated by a slightly modified CMOS process without any additional masking steps. Subthreshold slope, simulated threshold voltage Vt rolloff, and off-state leakage Ioff are comparable with control devices. The junction capacitance in SDODEL MOSFETs is found to be reduced by more than 40% compared to conventional MOSFETs. Measurement of ring oscillator speeds demonstrates that SDODEL MOSFETs enable a 15% reduction in gate delay td for each inverter stage. SDODEL transistors provide a low-cost alternative to SOI for reduction of S/D junction capacitance. © 2005 IEEE.
Source Title: IEEE Electron Device Letters
ISSN: 07413106
DOI: 10.1109/LED.2004.843215
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