Please use this identifier to cite or link to this item: https://doi.org/10.1063/1.1691170
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dc.titleQuantum mechanical modeling of gate capacitance and gate current in tunnel dielectric stack structures for nonvolatile memory application
dc.contributor.authorKoh, B.H.
dc.contributor.authorChim, W.K.
dc.contributor.authorNg, T.H.
dc.contributor.authorZheng, J.X.
dc.contributor.authorChoi, W.K.
dc.date.accessioned2014-10-07T04:35:28Z
dc.date.available2014-10-07T04:35:28Z
dc.date.issued2004-05-01
dc.identifier.citationKoh, B.H., Chim, W.K., Ng, T.H., Zheng, J.X., Choi, W.K. (2004-05-01). Quantum mechanical modeling of gate capacitance and gate current in tunnel dielectric stack structures for nonvolatile memory application. Journal of Applied Physics 95 (9) : 5094-5103. ScholarBank@NUS Repository. https://doi.org/10.1063/1.1691170
dc.identifier.issn00218979
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/82952
dc.description.abstractA self-consistent quantum mechanical (QM) numerical calculations, using an in-house developed charge quantization simulation program, were conducted to analyze the gate tunneling current and capacitance of metal-insulator- semiconductor (MIS) device with tunnel dielectric stack structures. The transmission probability through the dielectric stack structure was calculated by using a gate current density-gate voltage (Jg-Vg) simulation that uses a recursive method. It was shown that a physical model was used to fit with capacitance-voltage and Jg-Vg measurements on MIS devices with different single-layer dielectric and multilayered dielectric stack structures.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1063/1.1691170
dc.sourceScopus
dc.typeArticle
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.doi10.1063/1.1691170
dc.description.sourcetitleJournal of Applied Physics
dc.description.volume95
dc.description.issue9
dc.description.page5094-5103
dc.description.codenJAPIA
dc.identifier.isiut000220875400089
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