Please use this identifier to cite or link to this item: https://doi.org/10.1109/TED.2004.836544
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dc.titleMetal gate work function engineering on gate leakage of MOSFETs
dc.contributor.authorHou, Y.-T.
dc.contributor.authorLi, M.-F.
dc.contributor.authorLow, T.
dc.contributor.authorKwong, D.-L.
dc.date.accessioned2014-10-07T04:32:15Z
dc.date.available2014-10-07T04:32:15Z
dc.date.issued2004-11
dc.identifier.citationHou, Y.-T., Li, M.-F., Low, T., Kwong, D.-L. (2004-11). Metal gate work function engineering on gate leakage of MOSFETs. IEEE Transactions on Electron Devices 51 (11) : 1783-1789. ScholarBank@NUS Repository. https://doi.org/10.1109/TED.2004.836544
dc.identifier.issn00189383
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/82681
dc.description.abstractWe present a systematic study of tunneling leakage current in metal gate MOSFETs and how it is affected by the work function of the metal gate electrodes. Physical models used for simulations were corroborated by experimental results from SiO2 and HfO2 gate dielectrics with TaN electrodes. In bulk CMOS results show that, at the same capacitance equivalent oxide thickness (CET) at inversion, replacing a poly-Si gate by metal reduces the gate leakage appreciably by one to two orders of magnitude due to the elimination of polysilicon gate depletion. It is also found that the work function Φ B of a metal gate affects tunneling characteristics in MOSFETs. It is particularly significant when the transistor is biased at accumulation. Specifically, the increase of ΦB reduces the gate-to-channel tunneling in off-biased n-FET and the use of a metal gate with midgap ΦB results in a significant reduction of gate to source/drain extension (SDE) tunneling in both n- and p-FETs. Compared to bulk FET, double gate (DG) FET has much lower off-state leakage due to the smaller gate to SDE tunneling. This reduction in off-state leakage can be as much as three orders of magnitude when high-κ gate dielectric is used. Finally, the benefits of employing metal gate DG structure in future CMOS scaling are discussed. © 2004 IEEE.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/TED.2004.836544
dc.sourceScopus
dc.typeArticle
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.doi10.1109/TED.2004.836544
dc.description.sourcetitleIEEE Transactions on Electron Devices
dc.description.volume51
dc.description.issue11
dc.description.page1783-1789
dc.description.codenIETDA
dc.identifier.isiut000224656800005
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