Please use this identifier to cite or link to this item: https://doi.org/10.1109/LED.2005.853683
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dc.titleMechanism of positive-bias temperature instability in sub-1-nm TaN/HfN/HfO2 gate stack with low preexisting traps
dc.contributor.authorSa, N.
dc.contributor.authorKang, J.F.
dc.contributor.authorYang, H.
dc.contributor.authorLiu, X.Y.
dc.contributor.authorHe, Y.D.
dc.contributor.authorHan, R.Q.
dc.contributor.authorRen, C.
dc.contributor.authorYu, H.Y.
dc.contributor.authorChan, D.S.H.
dc.contributor.authorKwong, D.-L.
dc.date.accessioned2014-10-07T04:32:10Z
dc.date.available2014-10-07T04:32:10Z
dc.date.issued2005-09
dc.identifier.citationSa, N., Kang, J.F., Yang, H., Liu, X.Y., He, Y.D., Han, R.Q., Ren, C., Yu, H.Y., Chan, D.S.H., Kwong, D.-L. (2005-09). Mechanism of positive-bias temperature instability in sub-1-nm TaN/HfN/HfO2 gate stack with low preexisting traps. IEEE Electron Device Letters 26 (9) : 610-612. ScholarBank@NUS Repository. https://doi.org/10.1109/LED.2005.853683
dc.identifier.issn07413106
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/82674
dc.description.abstractIn this letter, the positive-bias temperature instability (PBTI) characteristics of a TaN/HfN/HfO2 gate stack with an equivalent oxide thickness (EOT) of 0.95 nm and low preexisting traps are studied. The negligible PBTI at room temperature, the so-called "turn-around" phenomenon, and the negative shifts of the threshold voltage (Vt) are observed. A modified reaction-diffusion (R-D) model, which is based on the electric stress induced defect generation (ESIDG) mechanism, is proposed to explain the above-mentioned PBTI characterestics. In this modified R-D model, PBTI is attributed to the electron-induced breaking of Si-O bonds at interfacial layer (IL) between HfO2 and Si substrate and the diffusion/drift of oxygen ions (O-) from Si-O bonds into HfO2 layer under positive-bias temperature stressing. The ESIDG mechanism is responsible for the breaking of Si-O bonds. The measured activation energy (Ea) is consistent with the one predicted by the ESIDG mechanism. © 2005 IEEE.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/LED.2005.853683
dc.sourceScopus
dc.subjectElectric stress-induced defect generation (ESIDG)
dc.subjectHigh-κ gate dielectric
dc.subjectPositive-bias temperature instability (PBTI)
dc.subjectReaction-diffusion (R-D) model
dc.typeArticle
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.doi10.1109/LED.2005.853683
dc.description.sourcetitleIEEE Electron Device Letters
dc.description.volume26
dc.description.issue9
dc.description.page610-612
dc.description.codenEDLED
dc.identifier.isiut000231577900004
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