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|Title:||Mechanism of positive-bias temperature instability in sub-1-nm TaN/HfN/HfO2 gate stack with low preexisting traps||Authors:||Sa, N.
|Keywords:||Electric stress-induced defect generation (ESIDG)
High-κ gate dielectric
Positive-bias temperature instability (PBTI)
Reaction-diffusion (R-D) model
|Issue Date:||Sep-2005||Citation:||Sa, N., Kang, J.F., Yang, H., Liu, X.Y., He, Y.D., Han, R.Q., Ren, C., Yu, H.Y., Chan, D.S.H., Kwong, D.-L. (2005-09). Mechanism of positive-bias temperature instability in sub-1-nm TaN/HfN/HfO2 gate stack with low preexisting traps. IEEE Electron Device Letters 26 (9) : 610-612. ScholarBank@NUS Repository. https://doi.org/10.1109/LED.2005.853683||Abstract:||In this letter, the positive-bias temperature instability (PBTI) characteristics of a TaN/HfN/HfO2 gate stack with an equivalent oxide thickness (EOT) of 0.95 nm and low preexisting traps are studied. The negligible PBTI at room temperature, the so-called "turn-around" phenomenon, and the negative shifts of the threshold voltage (Vt) are observed. A modified reaction-diffusion (R-D) model, which is based on the electric stress induced defect generation (ESIDG) mechanism, is proposed to explain the above-mentioned PBTI characterestics. In this modified R-D model, PBTI is attributed to the electron-induced breaking of Si-O bonds at interfacial layer (IL) between HfO2 and Si substrate and the diffusion/drift of oxygen ions (O-) from Si-O bonds into HfO2 layer under positive-bias temperature stressing. The ESIDG mechanism is responsible for the breaking of Si-O bonds. The measured activation energy (Ea) is consistent with the one predicted by the ESIDG mechanism. © 2005 IEEE.||Source Title:||IEEE Electron Device Letters||URI:||http://scholarbank.nus.edu.sg/handle/10635/82674||ISSN:||07413106||DOI:||10.1109/LED.2005.853683|
|Appears in Collections:||Staff Publications|
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