Junctionless II-gate transistor with indium gallium arsenide channel

Abstract

The fabrication and characterisation of a gate-first In 0.7Ga0.3As channel II-gate junctionless transistor by a CMOS-compatible top-down approach is reported for the first time. The structure uses a simple layer structure and process flow. 3D device simulation shows that the ?-gate structure can deplete the channel carriers more effectively compared with planar and tri-gate devices. The fabricated device with 200 nm gate length shows good transfer characteristics with a Ion/Ioff ratio of -104 and subthreshold swing of -210 mV/decade. The results indicate the suitability of the proposed structure for junctionless transistor operation. © The Institution of Engineering and Technology 2013.