Please use this identifier to cite or link to this item: https://doi.org/10.1088/0256-307X/22/8/055
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dc.titleHigh performance P-channel schottky barrier MOSFETs with self-aligned PtSi source/drain on thin film SOI substrate
dc.contributor.authorZhu, S.-Y.
dc.contributor.authorLi, M.-F.
dc.date.accessioned2014-10-07T04:29:34Z
dc.date.available2014-10-07T04:29:34Z
dc.date.issued2005-08-01
dc.identifier.citationZhu, S.-Y., Li, M.-F. (2005-08-01). High performance P-channel schottky barrier MOSFETs with self-aligned PtSi source/drain on thin film SOI substrate. Chinese Physics Letters 22 (8) : 2020-2022. ScholarBank@NUS Repository. https://doi.org/10.1088/0256-307X/22/8/055
dc.identifier.issn0256307X
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/82453
dc.description.abstractP-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with PtSi Schottky barrier source/drain, high-k gate dielectric and metal gate electrode were fabricated on a thin p-type silicon-on-insulator (SOI) substrate using a simplified low temperature process. The device works on a fully-depleted accumulation-mode and has an excellent electrical performance. It reaches I on/I off ratio of about 10 7, subthreshold swing of 65 mV/decade and saturation drain current of I ds ≤ 8.8 μA/μm at |V g-V th| ≤ |V d| ≤ 1 V for devices with the channel length 4.0 μm and the equivalent oxide thickness 2.0 nm. Compared to the corresponding bulk-Si counterparts, SOI p-SBMOSFETs have smaller off-state current due to reduction of the PtSi/Si contact area. © 2005 Chinese Physical Society and IOP Publishing Ltd.
dc.sourceScopus
dc.typeArticle
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.doi10.1088/0256-307X/22/8/055
dc.description.sourcetitleChinese Physics Letters
dc.description.volume22
dc.description.issue8
dc.description.page2020-2022
dc.identifier.isiutNOT_IN_WOS
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