Please use this identifier to cite or link to this item:
|Title:||A new polysilicon CMOS self-aligned double-gate TFT technology||Authors:||Xiong, Z.
Polysilicon thin-film transístor (TFT)
|Issue Date:||Dec-2005||Citation:||Xiong, Z., Liu, H., Zhu, C., Sin, J.K.O. (2005-12). A new polysilicon CMOS self-aligned double-gate TFT technology. IEEE Transactions on Electron Devices 52 (12) : 2629-2633. ScholarBank@NUS Repository. https://doi.org/10.1109/TED.2005.859686||Abstract:||In this paper, a new polysilicon CMOS self-aligned double-gate thin-film transistor (SA-DG TFT) technology is proposed and experimentally demonstrated. The self-alignment between the top- and bottom-gate is realized by a backlight exposure technique. The structure has an ultrathin channel region (300 Å) and a thick source/drain region. Experimental results show that this technology provides excellent current saturation due to a combination of the effective reduction in the drain Held and the full depletion of the ultrathin channel. Moreover, for n-channel devices, the SA-DG TFT has a 4.2 times higher on-current (Vgs = 20 V) as compared to the conventional single-gate TFT. Whereas for the p-channel devices, the SADG TFT has a 3.6 times higher on-current (Vgs = -20 V) compared to the conventional single-gate device. © 2005 IEEE.||Source Title:||IEEE Transactions on Electron Devices||URI:||http://scholarbank.nus.edu.sg/handle/10635/81892||ISSN:||00189383||DOI:||10.1109/TED.2005.859686|
|Appears in Collections:||Staff Publications|
Show full item record
Files in This Item:
There are no files associated with this item.
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.