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|Title:||Via design optimization for high speed device packaging||Authors:||Low, Hong-Guan
Iyer, Mahadevan K.
|Issue Date:||1998||Citation:||Low, Hong-Guan,Iyer, Mahadevan K.,Ooi, Ban-Leong,Leong, Mook-Seng (1998). Via design optimization for high speed device packaging. Proceedings of the Electronic Packaging Technology Conference, EPTC : 112-118. ScholarBank@NUS Repository.||Abstract:||This paper presents the design and electrical characterization of a circular via hole applied to single and multi chip modules. A typical strip line-to-strip line configuration incorporating the via hole is designed, modelled and simulated using a Mixed-Potential-Integration-Equation (MPIE)-based Field Solver, Maxwell Strata. This configuration is modelled on practical user-defined transmission line structure consisting of conductors and of finite conductivity. We investigated the effects of three critical parameters, via hole diameter, ground plane opening and via height on the frequency response. It is found that the via hole diameter should be minimized while the other two parameters should be maximized for better performance. This paper thus provides an useful optimization criteria of circular vias, given the practical limitations of manufacturing technologies.||Source Title:||Proceedings of the Electronic Packaging Technology Conference, EPTC||URI:||http://scholarbank.nus.edu.sg/handle/10635/81348|
|Appears in Collections:||Staff Publications|
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