Please use this identifier to cite or link to this item: https://doi.org/10.1016/S0026-2692(99)00112-3
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dc.titleSimple modelling of device speed in double-gate SOI MOSFETs
dc.contributor.authorRajendran, K.
dc.contributor.authorSamudra, G.
dc.date.accessioned2014-10-07T03:05:20Z
dc.date.available2014-10-07T03:05:20Z
dc.date.issued2000-04
dc.identifier.citationRajendran, K., Samudra, G. (2000-04). Simple modelling of device speed in double-gate SOI MOSFETs. Microelectronics Journal 31 (4) : 255-259. ScholarBank@NUS Repository. https://doi.org/10.1016/S0026-2692(99)00112-3
dc.identifier.issn00262692
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/81163
dc.description.abstractA new simple and accurate model for device speed is proposed for the first time in double-gate SOI MOSFETs. Simulation studies are done with physical and electrical parameters. Experimental results are compared with the results predicted by the analytical model and good agreement is seen. A record maximum value of transconductance in DG-SOI MOSFETs is achieved (1350 ms/mm at Lg = 0.05 μm and Tsi = 50 nm). It has been observed analytically that device speed higher than 1×107 cm/s is possible in DG-SOI MOSFETs at a lower silicon thickness and substrate concentration at Lg≤0.35 μm by appropriate modelling of parameters.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1016/S0026-2692(99)00112-3
dc.sourceScopus
dc.typeArticle
dc.contributor.departmentELECTRICAL ENGINEERING
dc.description.doi10.1016/S0026-2692(99)00112-3
dc.description.sourcetitleMicroelectronics Journal
dc.description.volume31
dc.description.issue4
dc.description.page255-259
dc.description.codenMICEB
dc.identifier.isiut000085193300005
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