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Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/81145
DC FieldValue
dc.titleSelf-timed system design technique
dc.contributor.authorTan, Y.K.
dc.contributor.authorLim, Y.C.
dc.date.accessioned2014-10-07T03:05:09Z
dc.date.available2014-10-07T03:05:09Z
dc.date.issued1990-03-01
dc.identifier.citationTan, Y.K.,Lim, Y.C. (1990-03-01). Self-timed system design technique. Electronics Letters 26 (5) : 284-286. ScholarBank@NUS Repository.
dc.identifier.issn00135194
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/81145
dc.description.abstractA new technique for the design of self-timed systems using a modified PCVSL (Precharged Cascode Voltage Switch Logic) circuit and a new handshaking protocol is presented. Our technique allows different data to be stored and computed in consecutive PCVSL pipeline stages simultaneously, resulting in a significant saving in silicon area and speed-up in fall-through delay.
dc.sourceScopus
dc.typeArticle
dc.contributor.departmentELECTRICAL ENGINEERING
dc.description.sourcetitleElectronics Letters
dc.description.volume26
dc.description.issue5
dc.description.page284-286
dc.description.codenELLEA
dc.identifier.isiutNOT_IN_WOS
Appears in Collections:Staff Publications

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