Please use this identifier to cite or link to this item:
|Title:||MOS device conductance modelling technique for an accurate and efficient mixed-mode simulation of CMOS circuits||Authors:||Samudra, G.
|Keywords:||CMOS integrated circuits
Semiconductor device models
|Issue Date:||1-Feb-1996||Citation:||Samudra, G.,Lee, T.K. (1996-02-01). MOS device conductance modelling technique for an accurate and efficient mixed-mode simulation of CMOS circuits. Electronics Letters 32 (3) : 264-265. ScholarBank@NUS Repository.||Abstract:||A new technique for modelling the conductance of an MOS device for the electrical logic simulation (the Elogic algorithm) of CMOS circuits is proposed. The technique is general and applicable to any analytic device current model. The Elogic algorithm allows the representation of a logic transition using a finite number of voltage steps and calculates time for each transition between the adjacent voltage steps. The examples show that the new technique can correctly predict a complete electrical waveform with a large voltage step of 1V to yield at least an order of magnitude computational time advantage over the circuit simulation.||Source Title:||Electronics Letters||URI:||http://scholarbank.nus.edu.sg/handle/10635/80755||ISSN:||00135194|
|Appears in Collections:||Staff Publications|
Show full item record
Files in This Item:
There are no files associated with this item.
checked on Mar 29, 2020
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.