Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/80746
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dc.titleModelling the degradation in the subthreshold characteristics of submicrometre LDD PMOSFETs under hot-carrier stressing
dc.contributor.authorQin, W.H.
dc.contributor.authorChim, W.K.
dc.contributor.authorChan, D.S.H.
dc.contributor.authorLou, C.L.
dc.date.accessioned2014-10-07T03:00:52Z
dc.date.available2014-10-07T03:00:52Z
dc.date.issued1998-05
dc.identifier.citationQin, W.H., Chim, W.K., Chan, D.S.H., Lou, C.L. (1998-05). Modelling the degradation in the subthreshold characteristics of submicrometre LDD PMOSFETs under hot-carrier stressing. Semiconductor Science and Technology 13 (5) : 453-459. ScholarBank@NUS Repository.
dc.identifier.issn02681242
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/80746
dc.description.abstractHot-carrier injection is observed increasingly to degrade the subthreshold characteristics with the scaling of LDD PMOSFETs. A physical subthreshold current model is applied to the fresh and hot-carrier-stressed submicrometre channel length devices. The channel length reduction is subsequently extracted. An empirical relationship is developed to characterize the degradation parameters as a function of stress time and channel length. With the use of this relationship, we can determine the device lifetime or predict the minimum allowable channel length (for a certain percentage of degradation and lifetime) that is applicable for a specific technology. The degradation of the PMOSFET subthreshold current, which imposes a major limit on device reliability for deep-submicron technology and low-power applications, is fully described by a physical analytical model.
dc.sourceScopus
dc.typeArticle
dc.contributor.departmentELECTRICAL ENGINEERING
dc.description.sourcetitleSemiconductor Science and Technology
dc.description.volume13
dc.description.issue5
dc.description.page453-459
dc.description.codenSSTEE
dc.identifier.isiut000073617400001
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