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|Title:||Measurement and simulation of hot carrier degradation in PMOSFET by gate capacitance||Authors:||Ling, C.H.
Samudra, Ganesh S.
Gan, Chock H.
|Issue Date:||May-1995||Citation:||Ling, C.H., Seah, B.P., Samudra, Ganesh S., Gan, Chock H. (1995-05). Measurement and simulation of hot carrier degradation in PMOSFET by gate capacitance. IEEE Transactions on Electron Devices 42 (5) : 928-934. ScholarBank@NUS Repository. https://doi.org/10.1109/16.381990||Abstract:||Hot carrier degradation in 0.8 μm channel length LDD p-channel MOS transistors is measured from gate capacitance before and after stress. Gate capacitance for the unstressed junction decreases, but that for the stressed junction it increases, after stress. The capacitance change is attributed to the trapping of electrons and the generation of interface traps at the Si-SiO2 interface. The effects are modeled by introducing a spatially uniform fixed charge of electrons Qn and Gaussian distributions (in energy) of both donor and acceptor interface traps Dit(E), centered at (Etd - Ev) = 0.25 eV and (Ec - Eta) = 0.3 eV respectively, at the Si-SiO2 interface. Simulation is carried out on the two dimensional device simulator MEDICI, based on device geometry and doping profile generated by TSUPREM-4 process simulator. Simulated results using Qn = -1 × 1012 cm-2 and Nit d = 0.25 × 1012 cm-2, Nit a = 1.0 × 1012 cm-2 for total donor and acceptor interface traps, are in excellent agreement with measurement. Logarithmic time degradation is observed from measurement of the increase in the overlap capacitance at zero gate bias. Time evolution of the degradation is simulated and demonstrated to be related to the uniform spatial growth of the damaged region at the interface near the drain junction.||Source Title:||IEEE Transactions on Electron Devices||URI:||http://scholarbank.nus.edu.sg/handle/10635/80705||ISSN:||00189383||DOI:||10.1109/16.381990|
|Appears in Collections:||Staff Publications|
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