Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/80489
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dc.titleGate-channel capacitance characteristics in the fully-depleted SOI MOSFET
dc.contributor.authorCheng, Z.-Y.
dc.contributor.authorLing, C.H.
dc.date.accessioned2014-10-07T02:58:05Z
dc.date.available2014-10-07T02:58:05Z
dc.date.issued2001-02
dc.identifier.citationCheng, Z.-Y., Ling, C.H. (2001-02). Gate-channel capacitance characteristics in the fully-depleted SOI MOSFET. IEEE Transactions on Electron Devices 48 (2) : 388-391. ScholarBank@NUS Repository.
dc.identifier.issn00189383
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/80489
dc.description.abstractA gate-channel capacitance minimum occurs in the capacitance-voltage (C-V) curve of a fully-depleted SOI MOSFET, when the front silicon surface is biased into accumulation while the back surface is maintained in strong inversion. This observation is explained in terms of a model based on the depletion width of the silicon film, taking into account the small accumulation and inversion layer thickness. A simple method is proposed to determine the flat-band potential in the SOI MOSFET.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/16.902743
dc.sourceScopus
dc.typeArticle
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.contributor.departmentELECTRICAL ENGINEERING
dc.description.sourcetitleIEEE Transactions on Electron Devices
dc.description.volume48
dc.description.issue2
dc.description.page388-391
dc.description.codenIETDA
dc.identifier.isiut000167017400030
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