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|Title:||Electron trapping and interface state generation in PMOSFET's: Results from gate capacitance||Authors:||Ling, C.H.||Issue Date:||1-Oct-1993||Citation:||Ling, C.H. (1993-10-01). Electron trapping and interface state generation in PMOSFET's: Results from gate capacitance. Japanese Journal of Applied Physics, Part 2: Letters 32 (10 A) : L1371-L1373. ScholarBank@NUS Repository.||Abstract:||Significant generation of hot-carrier induced donor and acceptor interface states in PMOSFET's is observed for the first time from gate-to-drain capacitance Cgd* s. Plotting the change ΔCgd* s against gate bias reveals two peaks, attributed to donor and acceptor states. A voltage on the drain displaces the donor peak by approximately the amount of the applied voltage, but the acceptor peak shifts by a fixed amount.||Source Title:||Japanese Journal of Applied Physics, Part 2: Letters||URI:||http://scholarbank.nus.edu.sg/handle/10635/80393||ISSN:||00214922|
|Appears in Collections:||Staff Publications|
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