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|Title:||DC voltage-voltage method to measure the interface traps in sub-micron MOSTs||Authors:||Jie, B.B.
|Issue Date:||Jul-1999||Citation:||Jie, B.B., Li, M.F., Chim, W.K., Chan, D.S.H., Lo, K.F. (1999-07). DC voltage-voltage method to measure the interface traps in sub-micron MOSTs. Semiconductor Science and Technology 14 (7) : 621-627. ScholarBank@NUS Repository. https://doi.org/10.1088/0268-1242/14/7/306||Abstract:||A dc voltage-voltage technique for the measurement of stress-generated interface traps in submicron MOSTs is demonstrated. This method uses the source-bulk-drain of a submicron MOST as an effective lateral bipolar transistor when the channel region is out of inversion under the control of the gate voltage Vgb. The emitter injects the minority carriers to the base region and the collector is open. The Vcb versus Vgb spectrum can be explained quantitatively in the spirit of the extended Ebers-Moll equations and interface trap SRH recombination. The spectrum shows clear information on stress-generated interface traps located at the collector-junction region. The new method has the advantages of simplicity, high sensitivity and wide application range to different device structures. A single effective interface trap at the source or drain side could be detected, and interface traps at the source side can be separated from those at the drain side by the new method. Moreover, we propose an improved gated-diode method to separate interface traps at the source side from those at the drain side.||Source Title:||Semiconductor Science and Technology||URI:||http://scholarbank.nus.edu.sg/handle/10635/80344||ISSN:||02681242||DOI:||10.1088/0268-1242/14/7/306|
|Appears in Collections:||Staff Publications|
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