Techniques for Crafting Customizable MPSoCS

Abstract

General-purpose processors offer high flexibility in terms of supporting wide range of applications. However, they hardly meet the high performance demands of computationally intensive applications. A common method for bridging the gap between flexibility and performance demands is to add customized accelerators into general-purpose processors. These customized accelerators are designed to explore the special features of different applications so that they can achieve dramatic speedups.

On the other hand, with the inevitable transition into the multi-core era, heterogeneity is emphasized to improve the overall efficiency of the application executions. Rather than integrating multiple simple cores within one chip, each of the cores could be tailored through customization techniques to meet the specific demands of the applications.

In this thesis, we propose a customized multiprocessor system-on-chip (MPSoC) architecture and the associated design automation tool-chain covering compiler supports and design space exploration techniques.

At the beginning, we first create a static heterogeneous MPSoC system by using custom functional units. The custom functional units are designed for accelerating different custom instruction sets. The limited chip area budget for customization and alternative customization choices present a challenging optimization problem for design space exploration. A dynamic programming algorithm is then designed to optimally retrieve the set of custom instructions for every task of the target application so as to have the highest speedup under the area constraint.

The rest of the thesis focuses on a reconfigurable heterogeneous MPSoC design where the customization is achieved through a reconfigurable fabric shared among the cores. We first focus on designing the appropriate reconfigurable fabric for customization. We propose a novel custom functional unit design that can be reconfigured to support most of the identified custom instructions across multiple application domains. The efficiency of the custom functional unit design is then evaluated by integrating it into the pipeline to form a just-in-time reconfigurable processor. We then design a coarse-grained reconfigurable array using the proposed custom functional unit as the primary processing element. Finally the customizable MPSoC architecture is completed by sharing the coarse-grained reconfigurable array among multiple cores.

We then study design automation problem for the newly designed customizable MPSoC architecture, in particular, the compiler support. We formulate the problem of mapping loop kernels onto the reconfigurable fabric as a graph minor containment problem. With the formalization, we design an efficient search algorithm adopted from the graph theory domain to solve the mapping problem.

As the final step of the design automation toolchain, we develop a design space exploration technique for mapping multi-threaded applications on the customizable MPSoC with shared reconfigurable fabric. In the presence of a shared reconfigurable fabric, the complexity of the design space is dramatically increased compared to the static approach. We propose an optimal solution based on dynamic programming that not only selects the appropriate customization for each core but also the appropriate reconfiguration points along the timeline to maximize performance while satisfying the area constraints of the shared reconfigurable fabric.