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Title: GPU code generation for ODE-based applications with phased shared-data access patterns
Authors: Hagiescu, A.
Bing, L.
Ramanathan, R.
Palaniappan, S.K.
Cui, Z.
Chattopadhyay, B.
Thiagarajan, P.S. 
Wong, W.-F. 
Keywords: Code generation
Memory hierarchy
Issue Date: Dec-2013
Citation: Hagiescu, A., Bing, L., Ramanathan, R., Palaniappan, S.K., Cui, Z., Chattopadhyay, B., Thiagarajan, P.S., Wong, W.-F. (2013-12). GPU code generation for ODE-based applications with phased shared-data access patterns. Transactions on Architecture and Code Optimization 10 (4) : -. ScholarBank@NUS Repository.
Abstract: We present a novel code generation scheme for GPUs. Its key feature is the platform-aware generation of a heterogeneous pool of threads. This exposes more data-sharing opportunities among the concurrent threads and reduces the memory requirements that would otherwise exceed the capacity of the on-chip memory. Instead of the conventional strategy of focusing on exposing as much parallelism as possible, our scheme leverages on the phased nature of memory access patterns found in many applications that exhibit massive parallelism. We demonstrate the effectiveness of our code generation strategy on a computational systems biology application. This application consists of computing a Dynamic Bayesian Network (DBN) approximation of the dynamics of signalling pathways described as a system of Ordinary Differential Equations (ODEs). The approximation algorithm involves (i) sampling many (of the order of a few million) times from the set of initial states, (ii) generating trajectories through numerical integration, and (iii) storing the statistical properties of this set of trajectories in Conditional Probability Tables (CPTs) of a DBN via a prespecified discretization of the time and value domains. The trajectories can be computed in parallel. However, the intermediate data needed for computing them, as well as the entries for the CPTs, are too large to be stored locally. Our experiments show that the proposed code generation scheme scales well, achieving significant performance improvements on three realistic signalling pathways models. These results suggest how our scheme could be extended to deal with other applications involving systems of ODEs. © 2013 ACM.
Source Title: Transactions on Architecture and Code Optimization
ISSN: 15443566
DOI: 10.1145/2555289.2555311
Appears in Collections:Staff Publications

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