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dc.titleHigh spatial resolution mapping of strain induced by the geometry configuration in nanoscaled devices
dc.contributor.authorToh, S.L.
dc.contributor.authorLoh, K.P.
dc.contributor.authorSee, K.S.
dc.contributor.authorBoothroyd, C.B.
dc.contributor.authorLi, K.
dc.contributor.authorLau, W.S.
dc.contributor.authorAng, C.H.
dc.contributor.authorChan, L.
dc.identifier.citationToh, S.L.,Loh, K.P.,See, K.S.,Boothroyd, C.B.,Li, K.,Lau, W.S.,Ang, C.H.,Chan, L. (2005). High spatial resolution mapping of strain induced by the geometry configuration in nanoscaled devices. Proceedings - Electrochemical Society PV 2005-05 : 561-568. ScholarBank@NUS Repository.
dc.description.abstractThe effects of the mechanical stress induced by the geometry configuration of the active regions for deep sub-micrometer complementary metal-oxide semiconductor (CMOS) field-effect transistors are investigated using two-dimensional contour mapping of the strain by convergent beam electron diffraction (CBED). The influence of two different source-drain diffusion lengths (L) on the strain distribution in the substrate and the transistor performance is reported. When L dimension is reduced, we have shown from the contour mapping that the compressive strain would spread from the edge of the trench structure into the silicon channel and the strain under the gate electrode is a result of superposition of the stresses from the adjacent shallow trench isolation (STI) structures. This would degrade the performance of the n-channel MOS devices. Increasing the L dimension greatly enhances the drive current by a reduction of the compressive strain underneath the gate stack.
dc.typeConference Paper
dc.description.sourcetitleProceedings - Electrochemical Society
dc.description.volumePV 2005-05
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