Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/72990
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dc.titleVLSI circuits for decomposing binary integers into signed power-of-two terms
dc.contributor.authorYong, Ching Lim
dc.contributor.authorLiu, Bede
dc.contributor.authorEvans, Joseph B.
dc.date.accessioned2014-06-19T05:14:17Z
dc.date.available2014-06-19T05:14:17Z
dc.date.issued1990
dc.identifier.citationYong, Ching Lim,Liu, Bede,Evans, Joseph B. (1990). VLSI circuits for decomposing binary integers into signed power-of-two terms. Proceedings - IEEE International Symposium on Circuits and Systems 3 : 2304-2307. ScholarBank@NUS Repository.
dc.identifier.issn02714310
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/72990
dc.description.abstractIf the coefficients of a digital filter are approximated by the sum of signed power-of-two terms, there will be a significant reduction in the area used and an improvement in the speed of custom implementations at the expense of a slight frequency-response deterioration. The authors present two circuits for extracting from a given integer a prescribed number of signed power-of-two terms whose sum is the closest approximation to that given integer. One of these circuits is bit-serial and the other is bit-parallel. Example layouts in a CMOS process are given.
dc.sourceScopus
dc.typeConference Paper
dc.contributor.departmentELECTRICAL ENGINEERING
dc.description.sourcetitleProceedings - IEEE International Symposium on Circuits and Systems
dc.description.volume3
dc.description.page2304-2307
dc.description.codenPICSD
dc.identifier.isiutNOT_IN_WOS
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