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|Title:||Single phase parallel power processing scheme with input-shunt power factor correction stage||Authors:||Srinivasan, Ramesh
|Issue Date:||1997||Citation:||Srinivasan, Ramesh,Oruganti, Ramesh (1997). Single phase parallel power processing scheme with input-shunt power factor correction stage. Proceedings of the International Conference on Power Electronics and Drive Systems 2 : 611-620. ScholarBank@NUS Repository.||Abstract:||A single-phase parallel power processing scheme with input-paralleled power factor correction stage is proposed. The input current in the proposed scheme is nearly-sinusoidal with power factor close to unity. This scheme is very attractive for systems with two or more independent loads, each requiring a ac-dc power converter. An example of one such system is a personal computer (the monitor and the CPU units). For such a system, the proposed scheme is both cost effective and efficient than the currently popular two-stage cascaded scheme. The scheme is implemented using a half-bride boost PFC stage, and is analyzed in detail. Analytical plots and expressions useful to a design engineer, have been developed. Switched and averaged model simulation results, and experimental results are also included. An efficiency of 93.78% at 90 V input, and a power factor of 0.999 were obtained experimentally. The possible circuit variations of the proposed scheme have also been identified.||Source Title:||Proceedings of the International Conference on Power Electronics and Drive Systems||URI:||http://scholarbank.nus.edu.sg/handle/10635/72922|
|Appears in Collections:||Staff Publications|
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