Please use this identifier to cite or link to this item:
https://scholarbank.nus.edu.sg/handle/10635/72880
DC Field | Value | |
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dc.title | Real time synthetic aperture radar (SAR) preprocessor design via three-dimensional modular filtering architecture | |
dc.contributor.author | Lim, Chan Hian | |
dc.contributor.author | Soon, Yeo Tat | |
dc.date.accessioned | 2014-06-19T05:13:01Z | |
dc.date.available | 2014-06-19T05:13:01Z | |
dc.date.issued | 1997 | |
dc.identifier.citation | Lim, Chan Hian,Soon, Yeo Tat (1997). Real time synthetic aperture radar (SAR) preprocessor design via three-dimensional modular filtering architecture. International Geoscience and Remote Sensing Symposium (IGARSS) 1 : 487-489. ScholarBank@NUS Repository. | |
dc.identifier.uri | http://scholarbank.nus.edu.sg/handle/10635/72880 | |
dc.description.abstract | Synthetic Aperture Radar (SAR) systems are increasingly demanding for real real-time performance. As part of an effort to develop a real-time Range-Doppler digital SAR processor to produce image maps of that scanned area immediately as raw data are collected, this paper describes the conceptual architecture design for a high-speed front-end video pre-filtering. The evolved architecture consists of richly interconnected planes of novelly-adapted Modified Transverse FIR parallel tapped delay elements. Both the range and azimuth prefilterings are performed simultaneously in a continuous input-output flow without the need to worry about corner turning caused by azimuth preprocessing on data samples that are collected in the range direction. | |
dc.source | Scopus | |
dc.type | Conference Paper | |
dc.contributor.department | ELECTRICAL ENGINEERING | |
dc.description.sourcetitle | International Geoscience and Remote Sensing Symposium (IGARSS) | |
dc.description.volume | 1 | |
dc.description.page | 487-489 | |
dc.description.coden | IGRSE | |
dc.identifier.isiut | NOT_IN_WOS | |
Appears in Collections: | Staff Publications |
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