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|Title:||Pre-breakdown charge trapping in ESD stressed thin MOS gate oxides||Authors:||Teh, G.L.
|Issue Date:||1997||Citation:||Teh, G.L.,Chim, W.K. (1997). Pre-breakdown charge trapping in ESD stressed thin MOS gate oxides. Proceedings of the International Symposium on the Physical & Failure Analysis of Integrated Circuits, IPFA : 156-161. ScholarBank@NUS Repository.||Abstract:||A change in the pre-breakdown trap generation under constant voltage stressing (CVS) was observed in thin oxides subjected to positive ESD pulses applied to the gate electrode. Results show that ESD pulses will create both positive and neutral traps, the latter being highly susceptible to electron trapping. It was also found that the damage in oxides subjected to low-level ESD events (i.e. number of ESD pulses less than 20) can be annealed out electrically. These annealed oxides show electrical characteristics that are identical to that of a non-ESD-stressed oxide.||Source Title:||Proceedings of the International Symposium on the Physical & Failure Analysis of Integrated Circuits, IPFA||URI:||http://scholarbank.nus.edu.sg/handle/10635/72867|
|Appears in Collections:||Staff Publications|
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