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|Title:||Design optimization of power MOSFET for high frequency synchronous rectification||Authors:||Liang, Y.C.
|Issue Date:||1993||Citation:||Liang, Y.C.,Oruganti, R.,Oh, T.B. (1993). Design optimization of power MOSFET for high frequency synchronous rectification. IECON Proceedings (Industrial Electronics Conference) 2 : 767-772. ScholarBank@NUS Repository.||Abstract:||Synchronous rectifiers used in high frequency, low output voltage applications are power MOSFETs specially designed to replace the usual output Schottky diodes in order to reduce converter losses. This paper deals with the analysis and design optimization of a synchronous rectifier suitable for applications of 1 to 10 MHz switching power supplies. Three different MOSFET structures were studied and evaluated through detailed 2-dimensional device simulations. The process parameters are optimized against three major performance parameters, namely (1) the recovery time of the body diode, (2) the product of on-state resistance and input capacitance and (3) the breakdown voltage of the body diode. Based on the evaluation, the UMOS structure was selected for further work. The final design optimization of the UMOS was then carried out and an optimized device is presented as the final design.||Source Title:||IECON Proceedings (Industrial Electronics Conference)||URI:||http://scholarbank.nus.edu.sg/handle/10635/72570||ISBN:||0780308913|
|Appears in Collections:||Staff Publications|
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