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|Title:||Simulation of multiple gate FinFET device gate capacitance and performance with gate length and pitch scaling||Authors:||Zhao, H.
|Issue Date:||2007||Citation:||Zhao, H.,Agrawal, N.,Javier, R.,Rustagi, S.C.,Jurczak, M.,Yeo, Y.-C.,Samudra, G.S. (2007). Simulation of multiple gate FinFET device gate capacitance and performance with gate length and pitch scaling. International Conference on Simulation of Semiconductor Processes and Devices, SISPAD : 252-255. ScholarBank@NUS Repository. https://doi.org/10.1109/SISPAD.2006.282883||Abstract:||In this work, we simulate silicon-on-insulator (SOI) multiple gate FinFET (MuGFET) with the design targeting for the ITRS 2004 specifications for NMOSFET. A detailed fully 3D simulation and analysis of the parasitic capacitances is performed for the first time to study the impact of scaling and pitch spacing. Unlike planar devices, FinFET scaling does not always result in a straightforward performance improvement due to the current crowding effect and series resistance. © 2006 IEEE.||Source Title:||International Conference on Simulation of Semiconductor Processes and Devices, SISPAD||URI:||http://scholarbank.nus.edu.sg/handle/10635/71782||ISBN:||1424404045||DOI:||10.1109/SISPAD.2006.282883|
|Appears in Collections:||Staff Publications|
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