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|Title:||SFPGA - A scalable switch based FPGA architecture and design methodology||Authors:||Fernando, S.
|Issue Date:||2008||Citation:||Fernando, S.,Chen, X.,Ha, Y. (2008). SFPGA - A scalable switch based FPGA architecture and design methodology. Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL : 95-100. ScholarBank@NUS Repository. https://doi.org/10.1109/FPL.2008.4629914||Abstract:||The poor scalability of current mesh-based FPGA interconnection networks is impeding our attempts to build next-generation FPGA of larger logic capacity. A few alternative interconnection network architectures have been proposed for future FPGAs, but they still have several design challenges that need to be addressed. In this paper, we propose sFPGA, a scalable FPGA architecture, which is a hybrid between hierarchical interconnection and Network-on-Chip. The logic resources in sFPGA are organized into an array of logic tiles. The tiles are connected by a hierarchical network of switches, which route data packets over the network. In addition, we have proposed a design flow for sFPGA which integrates current design flows seamlessly. By doing a case study in our emulation prototype, we have validated our sF-PGA design flow. ©2008 IEEE.||Source Title:||Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL||URI:||http://scholarbank.nus.edu.sg/handle/10635/71757||ISBN:||9781424419616||DOI:||10.1109/FPL.2008.4629914|
|Appears in Collections:||Staff Publications|
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