Partial SOI superjunction power LDMOS for PIC application

Abstract

An enabling superjunction device technology, which is fully integrated on the Partial Silicon on Insulator (PSOI) platform using the bulk silicon substrate, is proposed and fabricated. The proposed technology has the potential to eliminate the substrate assisted depletion. It enables the implementation of lateral superjunction power MOSFET (SJ LDMOS) on bulk silicon substrate without sacrificing its thermal performance. In this paper, the approach was demonstrated successfully on both p-i-n diode and planar gate SJ LDMOS devices. The proposed technology has enabled the fabrication of SJ Power Integrated Circuits (PIC) on the bulk silicon substrate for future automotive power electronics applications.