Please use this identifier to cite or link to this item:
|Title:||M-V MOSFETs: Surface passivation, source/drain and channel strain engineering, self-aligned contact metallization||Authors:||Yeo, Y.-C.
|Issue Date:||2011||Citation:||Yeo, Y.-C.,Chin, H.-C.,Gong, X.,Guo, H.,Zhang, X. (2011). M-V MOSFETs: Surface passivation, source/drain and channel strain engineering, self-aligned contact metallization. ECS Transactions 35 (3) : 351-361. ScholarBank@NUS Repository.||Abstract:||In this paper, we discuss the research and development of gate-stack, source/drain, and contact process modules for high-mobility III-V n-MOSFETs. Work performed in our research group will be reviewed. Surface passivation technologies were developed for forming gate stacks on III-V materials such as GaAs and InGaAs. In situ doped lattice-mismatched source/drain (S/D) stressors were integrated in InGaAs MOSFETs with for reduction of S/D series resistance as well as for channel strain engineering. High-stress liner stressor was also used for inducing strain in the channel of InGaAs FETs. Several salicide-like process technologies were developed for self-aligned contact metallization in III-V MOSFETs. A III-V multiple-gate transistor with lightly doped fin with retrograde doping for suppression of short channel effects was demonstrated.||Source Title:||ECS Transactions||URI:||http://scholarbank.nus.edu.sg/handle/10635/71083||ISBN:||9781566778640||ISSN:||19385862|
|Appears in Collections:||Staff Publications|
Show full item record
Files in This Item:
There are no files associated with this item.
checked on Apr 12, 2021
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.