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|Title:||Minimizing power consumption of spatial division based networks-on-chip using multi-path and frequency reduction||Authors:||Wang, S.H.
|Keywords:||mixed integer linear programming
Spatial division multiplexing
|Issue Date:||2012||Citation:||Wang, S.H.,Das, A.,Kumar, A.,Corporaal, H. (2012). Minimizing power consumption of spatial division based networks-on-chip using multi-path and frequency reduction. Proceedings - 15th Euromicro Conference on Digital System Design, DSD 2012 : 576-583. ScholarBank@NUS Repository. https://doi.org/10.1109/DSD.2012.85||Abstract:||With an increasing number of processing elements being integrated on a single die, networks-on-chip (NoCs) are emerging as a significant contributor to overall chip power consumption. While some solutions have been proposed to reduce this power consumption, none of them can be applied to spatial division multiplexing (SDM)-based NoCs. In this paper, we introduce a method to minimize the power consumption of an SDM-based NoC by frequency minimization, while still satisfying the bandwidth requirements. The problem is integrated with the connection-routing problem which is modeled as a mixed-integer quadratic constrained problem (MIQCP). However, solving this MIQCP formulation directly using existing solvers is infeasible for large use-cases. We propose a two-step approach by first computing the minimum feasible frequency for the entire network taking bandwidth of all connections into consideration. This first step reduces the frequency-minimization-routing MIQCP problem into a routing-only mixed-integer linear programming (MILP) problem. In the second step, this MILP problem is solved using a standard ILP solver. Two other techniques are proposed to solve the routing and frequency minimization problem. Experiments are performed with synthetic examples and a case-study with JPEG decoder to evaluate the performance and results of the three methods. MILP-based approach achieves up to 55% power reduction as compared to the other methods albeit at the cost of higher execution time. © 2012 IEEE.||Source Title:||Proceedings - 15th Euromicro Conference on Digital System Design, DSD 2012||URI:||http://scholarbank.nus.edu.sg/handle/10635/70948||ISBN:||9780769547985||DOI:||10.1109/DSD.2012.85|
|Appears in Collections:||Staff Publications|
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