Please use this identifier to cite or link to this item: https://doi.org/10.1109/TSM.2004.831536
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dc.titleIn situ fault detection of wafer warpage in microlithography
dc.contributor.authorHo, W.K.
dc.contributor.authorTay, A.
dc.contributor.authorZhou, Y.
dc.contributor.authorYang, K.
dc.date.accessioned2014-06-19T03:13:41Z
dc.date.available2014-06-19T03:13:41Z
dc.date.issued2004-08
dc.identifier.citationHo, W.K., Tay, A., Zhou, Y., Yang, K. (2004-08). In situ fault detection of wafer warpage in microlithography. IEEE Transactions on Semiconductor Manufacturing 17 (3) : 402-407. ScholarBank@NUS Repository. https://doi.org/10.1109/TSM.2004.831536
dc.identifier.issn08946507
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/70573
dc.description.abstractWafer warpage is common in microelectronics processing. Warped wafers can affect device performance, reliability and linewidth control in various processing steps. We proposed in this paper an in situ fault detection technique for wafer warpage in microlithography. Early detection will minimize cost and processing time. Based on first principle thermal modeling, we are able to detect warpage fault from available temperature measurements. Experimental results demonstrate the feasibility and repeatability of the approach. The proposed approach is applicable to other semiconductor substrates.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/TSM.2004.831536
dc.sourceScopus
dc.subjectFault detection
dc.subjectMicrolithography
dc.subjectTemperature measurement
dc.subjectWafer warpage
dc.typeConference Paper
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.doi10.1109/TSM.2004.831536
dc.description.sourcetitleIEEE Transactions on Semiconductor Manufacturing
dc.description.volume17
dc.description.issue3
dc.description.page402-407
dc.description.codenITSME
dc.identifier.isiut000223187900022
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