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Please use this identifier to cite or link to this item: https://doi.org/10.1109/IPFA.2009.5232561
DC FieldValue
dc.titleImproved retention and cycling characteristics of MONOS memory using charge-trapping engineering
dc.contributor.authorChin, A.
dc.contributor.authorLin, S.H.
dc.contributor.authorYang, H.J.
dc.contributor.authorTsai, C.Y.
dc.contributor.authorYeh, F.S.
dc.contributor.authorLiao, C.C.
dc.contributor.authorLi, M.-F.
dc.date.accessioned2014-06-19T03:13:30Z
dc.date.available2014-06-19T03:13:30Z
dc.date.issued2009
dc.identifier.citationChin, A.,Lin, S.H.,Yang, H.J.,Tsai, C.Y.,Yeh, F.S.,Liao, C.C.,Li, M.-F. (2009). Improved retention and cycling characteristics of MONOS memory using charge-trapping engineering. Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA : 641-645. ScholarBank@NUS Repository. <a href="https://doi.org/10.1109/IPFA.2009.5232561" target="_blank">https://doi.org/10.1109/IPFA.2009.5232561</a>
dc.identifier.isbn9781424439102
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/70557
dc.description.abstractThe shallow trap energy in SONOS Charge-Trapping Flash (CTF) is the fundamental challenge for required good retention, especially at elevated temperatures. Although the high temperature retention can be improved by BE-SONOS, this is traded off the slow erase speed. To address these issues, we have fabricated a new Charge-Trapping-Engineered Flash (CTEF) using deep trapping high- dielectric to replace Si3N4. At l500C, the CTEF device shows a large 5.6 V initial memory window and a 3.8 V 10-year extrapolated retention for 4-bits/cell MLC, under very fast 100 sand ±16 V program/erase condition. © 2009 IEEE.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/IPFA.2009.5232561
dc.sourceScopus
dc.typeConference Paper
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.doi10.1109/IPFA.2009.5232561
dc.description.sourcetitleProceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
dc.description.page641-645
dc.identifier.isiutNOT_IN_WOS
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