Please use this identifier to cite or link to this item: https://doi.org/10.1109/ICSICT.2010.5667643
Title: III-V MOSFETs: Surface passivation for gate stack, source/drain and channel strain engineering, self-aligned contact metallization
Authors: Yeo, Y.-C. 
Chin, H.-C.
Gong, X.
Guo, H.
Zhang, X.
Issue Date: 2010
Citation: Yeo, Y.-C.,Chin, H.-C.,Gong, X.,Guo, H.,Zhang, X. (2010). III-V MOSFETs: Surface passivation for gate stack, source/drain and channel strain engineering, self-aligned contact metallization. ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings : 1298-1301. ScholarBank@NUS Repository. https://doi.org/10.1109/ICSICT.2010.5667643
Abstract: In this paper, we discuss the research and development of several key process modules for realizing high-mobility III-V n-MOSFETs. Interface passivation technologies were developed to realize high quality gate stacks on III-V. InGaAs MOSFETs with in situ doped lattice-mismatched source/drain (S/D) stressors were demonstrated for reduction of S/D series resistance as well as channel strain engineering. InGaAs FETs with high-stress liner stressor were also realized. A CMOS-compatible salicide-like process was developed for self-aligned contact metallization. We also explore the integration of III-V on Si platform for potential device integration. ©2010 IEEE.
Source Title: ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings
URI: http://scholarbank.nus.edu.sg/handle/10635/70520
ISBN: 9781424457984
DOI: 10.1109/ICSICT.2010.5667643
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