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|Title:||High throughput area-efficient SoC-based forward/inverse integer transforms for H.264/AVC||Authors:||Do, T.T.T.
|Issue Date:||2010||Citation:||Do, T.T.T.,Le, T.M. (2010). High throughput area-efficient SoC-based forward/inverse integer transforms for H.264/AVC. ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems : 4113-4116. ScholarBank@NUS Repository. https://doi.org/10.1109/ISCAS.2010.5537614||Abstract:||In this paper, high throughput area-efficient system-on-chip-based (SoC) forward/inverse integer transform (FIT/IIT) modules for H.264/AVC are proposed. High throughput can be achieved by pipelining quantization/rescaling and FIT/IIT blocks; while efficient area is possible by reusing architecture of all four transforms and using buffers for smoothening multiplications and reducing the number of multipliers and quantization/rescaling hardware. With the support of an Application Specific Instruction Processor (ASIP) and 2 built-in-RAM DMACs, the proposed FIT/IIT modules can perform both 4x4 and 8x8 transforms, and 2x2 and 4x4 Hadamard transforms of DC coefficients. Compared to the reported designs in 0.18 μm technology, the proposed FIT and IIT modules score higher Data Throughput per Unit Area (DTUA), and operate on each 8x8 block including I/O in 8 cycles, at 162.1 and 230.9 MHz, respectively. ©2010 IEEE.||Source Title:||ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems||URI:||http://scholarbank.nus.edu.sg/handle/10635/70474||ISBN:||9781424453085||DOI:||10.1109/ISCAS.2010.5537614|
|Appears in Collections:||Staff Publications|
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