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|Title:||Ge MOS transistor technology and reliability||Authors:||Zhu, C.||Issue Date:||2007||Citation:||Zhu, C. (2007). Ge MOS transistor technology and reliability. ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings : 128-131. ScholarBank@NUS Repository. https://doi.org/10.1109/ICSICT.2006.306095||Abstract:||In this paper, recent developments in Ge MOS transistor technology and reliability are reviewed. High-k gate stack formation on Ge substrate is first addressed with emphasis on silicon surface passivation. Ge source/drain junction formation of using laser thermal annealing with small dopant loss is then discussed. With high performance Ge p- and n-channel MOSFETs, BTI and charge trapping are characterized. © 2006 IEEE.||Source Title:||ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings||URI:||http://scholarbank.nus.edu.sg/handle/10635/70410||ISBN:||1424401615||DOI:||10.1109/ICSICT.2006.306095|
|Appears in Collections:||Staff Publications|
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