Please use this identifier to cite or link to this item:
|Title:||Fast median filtering algorithm based on FPGA||Authors:||Wei, P.
|Keywords:||Fast median filtering
|Issue Date:||2010||Citation:||Wei, P.,Zhang, L.,Ma, C.,Yeo, T.S. (2010). Fast median filtering algorithm based on FPGA. International Conference on Signal Processing Proceedings, ICSP : 426-429. ScholarBank@NUS Repository. https://doi.org/10.1109/ICOSP.2010.5655365||Abstract:||Median filter has good capabilities for reducing a variety kind of random noise, and causes less ambiguity than linear smoothing filters under same processing size. In order to suppress the impulse noise of digital video signal and meet the system's needs of real-time, it is of great significance to do fast filtering of image based on hardware. By analyzing the common 3×3 filtering window's mathematical model, this paper proposes a fast median filtering algorithm based on field programmable gate array (FPGA) and the scheme design. According to the characteristics of parallel structures and its suitable for pipeline design of FPGA. VHDL and schematic design are used in this paper to design the implement circuit. Quartus II is used for timing simulation. The results show that it can filter the impulse noise in real time and improves the quality of image. © 2010 IEEE.||Source Title:||International Conference on Signal Processing Proceedings, ICSP||URI:||http://scholarbank.nus.edu.sg/handle/10635/70306||ISBN:||9781424458981||DOI:||10.1109/ICOSP.2010.5655365|
|Appears in Collections:||Staff Publications|
Show full item record
Files in This Item:
There are no files associated with this item.
checked on Jun 25, 2022
checked on Jun 23, 2022
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.