Please use this identifier to cite or link to this item: https://doi.org/10.1109/FPL.2007.4380660
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dc.titleFast and accurate interval-based timing estimator for variability-aware FPGA physical synthesis tools
dc.contributor.authorLee, C.S.
dc.contributor.authorLoke, W.T.
dc.contributor.authorZhang, W.
dc.contributor.authorHa, Y.
dc.date.accessioned2014-06-19T03:10:29Z
dc.date.available2014-06-19T03:10:29Z
dc.date.issued2007
dc.identifier.citationLee, C.S., Loke, W.T., Zhang, W., Ha, Y. (2007). Fast and accurate interval-based timing estimator for variability-aware FPGA physical synthesis tools. Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL : 279-284. ScholarBank@NUS Repository. https://doi.org/10.1109/FPL.2007.4380660
dc.identifier.isbn1424410606
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/70296
dc.description.abstractProcess variations of deep sub-micron technologies have created significant timing uncertainty. This generates the need for a new variability-aware physical synthesis tool for Field-Programmable Gate-Arrays (FPGAs). Ideally, variability-aware tools should be able to perform both timing variability estimation during the synthesis and timing variability analysis after the synthesis. Statistical static timing analysis (SSTA) methods are developed to perform timing variability analysis, but are computationally expensive and not fast enough. We propose a fast and accurate interval-based method for the timing variability estimation. This method uses correlation-aware affine intervals instead of probability density distributions to model timing uncertainties. Our model estimates the mean of timing variation within an accuracy of 99.9% and an average range looseness of -7.5% for the Monte Carlo (MC) model. A speed-up of about 80X and 4900X is achieved for the Correlation Aware Canonical Timing (CACT) model and MC model respectively. © 2007 IEEE.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/FPL.2007.4380660
dc.sourceScopus
dc.typeConference Paper
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.doi10.1109/FPL.2007.4380660
dc.description.sourcetitleProceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL
dc.description.page279-284
dc.identifier.isiut000252360200044
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