Please use this identifier to cite or link to this item: https://doi.org/10.1109/IECON.2005.1569046
DC FieldValue
dc.titleExperimental verification of a dual single-input single-output model of a three-phase boost-type PWM rectifier
dc.contributor.authorYin, B.
dc.contributor.authorOruganti, R.
dc.contributor.authorPanda, S.K.
dc.contributor.authorBhat, A.K.S.
dc.date.accessioned2014-06-19T03:10:01Z
dc.date.available2014-06-19T03:10:01Z
dc.date.issued2005
dc.identifier.citationYin, B.,Oruganti, R.,Panda, S.K.,Bhat, A.K.S. (2005). Experimental verification of a dual single-input single-output model of a three-phase boost-type PWM rectifier. IECON Proceedings (Industrial Electronics Conference) 2005 : 1030-1035. ScholarBank@NUS Repository. <a href="https://doi.org/10.1109/IECON.2005.1569046" target="_blank">https://doi.org/10.1109/IECON.2005.1569046</a>
dc.identifier.isbn0780392523
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/70255
dc.description.abstractThis paper proposes a simple dual SISO (single-input -single-output) model for a three-phase boost-type PWM rectifier under balanced line voltage conditions. In the proposed model, the q-axis model is a first order linear system determining the power factor regulation, whereas the d-axis model, which is shown to be similar to a traditional dc-dc boost converter, is a second-order non-linear system determining the power delivery. It is much easier to analyze and control a complex three-phase PWM rectifier using the proposed model. In addition, the complex non-minimum phase feature inherent in a ac-to-dc rectifier becomes a simple right half plane (RHP) zero appearing in the small-signal control-to-output transfer function of the proposed d-axis model. The knowledge of RHP zero's location is vital to the successful design of a stable controller for the rectifier, as the presence of the RHP zero imposes a strict limit on the achievable closed loop performance. The validity of the proposed model is verified through experimental Bode Plot results obtained using a hardware prototype. © 2005 IEEE.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/IECON.2005.1569046
dc.sourceScopus
dc.typeConference Paper
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.doi10.1109/IECON.2005.1569046
dc.description.sourcetitleIECON Proceedings (Industrial Electronics Conference)
dc.description.volume2005
dc.description.page1030-1035
dc.description.codenIEPRE
dc.identifier.isiutNOT_IN_WOS
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