Please use this identifier to cite or link to this item:
|Title:||Evaluation of IBIS modelling techniques for signal integrity simulations without and with package parasitics||Authors:||Ji, Y.
|Issue Date:||2010||Citation:||Ji, Y.,Mouthaan, K.,Venkatarayalu, N.V. (2010). Evaluation of IBIS modelling techniques for signal integrity simulations without and with package parasitics. 2010 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2010 : -. ScholarBank@NUS Repository. https://doi.org/10.1109/EDAPS.2010.5683003||Abstract:||Input/Output Buffer Information Specification (IBIS) models are widely used in signal integrity analysis because of their ability to protect proprietary information and to reduce simulation time when compared to full SPICE simulations. Generation of IBIS models with I/V and V/T data from a full SPICE model of a typical digital buffer without and with package parasitics is investigated in this paper. Several different IBIS model generation strategies to incorporate package effects are validated with the full SPICE model in order to provide a suitable approach. In addition, the accuracy of IBIS simulations in HSPICE and ADS is investigated.||Source Title:||2010 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2010||URI:||http://scholarbank.nus.edu.sg/handle/10635/70215||ISBN:||9781424490684||DOI:||10.1109/EDAPS.2010.5683003|
|Appears in Collections:||Staff Publications|
Show full item record
Files in This Item:
There are no files associated with this item.
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.