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https://scholarbank.nus.edu.sg/handle/10635/70097
DC Field | Value | |
---|---|---|
dc.title | Effects of electron-beam lithography on thin gate oxide reliability | |
dc.contributor.author | Chong, P.F. | |
dc.contributor.author | Cho, B.J. | |
dc.contributor.author | Chor, E.F. | |
dc.contributor.author | Joo, M.S. | |
dc.date.accessioned | 2014-06-19T03:08:12Z | |
dc.date.available | 2014-06-19T03:08:12Z | |
dc.date.issued | 2001 | |
dc.identifier.citation | Chong, P.F.,Cho, B.J.,Chor, E.F.,Joo, M.S. (2001). Effects of electron-beam lithography on thin gate oxide reliability. Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA : 55-58. ScholarBank@NUS Repository. | |
dc.identifier.uri | http://scholarbank.nus.edu.sg/handle/10635/70097 | |
dc.description.abstract | The effects of E-beam lithography on thin gate oxide reliability were studied. For leakage currents and quasi-breakdown (QB) measurements, MOS capacitors on p-type silicon wafers with 3.5 and 4.5 nm gate oxides were used. Constant E-beam currents in the range of nA-μ were used to investigate the dependence of beam current on oxide degradation. Results confirm that E-beam lithography technologies can be implemented on thin oxide without significant impact on the long-term reliability. | |
dc.source | Scopus | |
dc.type | Conference Paper | |
dc.contributor.department | ELECTRICAL & COMPUTER ENGINEERING | |
dc.description.sourcetitle | Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA | |
dc.description.page | 55-58 | |
dc.identifier.isiut | NOT_IN_WOS | |
Appears in Collections: | Staff Publications |
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